Soic chip architecture

ABSTRACT

A device, such as a computer system, includes an interconnection device die and at least two additional device dice. The additional device dies can be system on integrated chip (SOIC) dies laying face to face (F2F) on the interconnection device die. The interconnection device die includes electrical connectors on one surface, enabling connection to and/or among the additional device dice. The interconnection device die includes at least one redistribution circuit structure, which may be an integrated fan out (InFO) structure, and at least one through-silicon via (TSV). The TSV enables connection between a signal line, power line or ground line, from an opposite surface of the interconnection device die to the redistribution circuit structure and/or electrical connectors. At least one of the additional dice can be a three-dimensional integrated circuit (3DIC) die with face to back (F2B) stacking.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a divisional of U.S. patent application Ser.No. 16/562,540 filed Sep. 6, 2019, titled “SOIC Chip Architecture,”which claims the benefit of U.S. Provisional Patent Appl. No.62/772,380, filed Nov. 28, 2018, titled “SOIC AI Chip Architecture,”both of which are incorporated herein by reference in their entireties.

BACKGROUND

Advances in the big data and artificial intelligence (AI) industrieshave enabled natural language and cognitive technology capabilities andempowered information technology to perform tasks traditionallyperformed by humans. Such technologies permit consumers to off loadtasks to such devices and help companies improve the quality ofservices, reduce response time for customers, and reduce costs. However,the increasing complexity and breadth of AI and big data operationsstrain existing computer systems with respect to memory access,real-time service, and power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the common practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofillustration and discussion.

FIGS. 1A to 1C are illustrations of an exemplary device die in crosssectional views that incorporate electrical connectors, according tosome embodiments.

FIG. 2 is an illustration of an electrical connector or a device die, inaccordance with some embodiments.

FIGS. 3A and 3B are illustrations of electrical connectors of a devicedie, in accordance with some embodiments.

FIGS. 4A and 4B are illustrations of an exemplary SOIC AI chiparchitecture layout that includes a device die, according to someembodiments.

FIG. 5 is an illustration of a CPU farm connected through a device die,according to some embodiments.

FIG. 6 is an illustration of an SOIC package optimized for an AI or bigdata architecture, according to some embodiments.

FIG. 7 is a flow chart of a method for the fabrication of an SOIC chiparchitecture, according to some embodiments.

FIG. 8 is a flow chart of a method for the fabrication of a 3Dthree-dimensional system on integrated chip structure, according to someembodiments.

The accompanying drawings, which are incorporated herein and form partof the specification, illustrate the present disclosure and, togetherwith the description, further serve to explain the principles of thedisclosure and to enable a person skilled in the relevant art to makeand use the disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. In addition, the presentdisclosure may repeat reference numerals and/or letters in the variousexamples. This repetition does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

It is noted that references in the specification to “one embodiment,”“an embodiment,” “an example embodiment,” “exemplary,” etc., indicatethat the embodiment described may include a particular feature,structure, or characteristic, but every embodiment may not necessarilyinclude the particular feature, structure, or characteristic. Moreover,such phrases do not necessarily refer to the same embodiment. Further,when a particular feature, structure or characteristic is described inconnection with an embodiment, it would be within the knowledge of oneskilled in the art to effect such feature, structure or characteristicin connection with other embodiments whether or not explicitlydescribed.

It is to be understood that the phraseology or terminology herein is forthe purpose of description and not of limitation, such that theterminology or phraseology of the present specification is to beinterpreted by those skilled in relevant art(s) in light of theteachings herein.

As used herein, the term “about” indicates the value of a given quantitythat can vary based on a particular technology node associated with thesubject semiconductor device. In some embodiments, based on theparticular technology node, the term “about” can indicate a value of agiven quantity that varies within, for example, 5% of the value (e.g.,±1%, ±2%, ±3%, ±4%, or ±5% of the value).

Embodiments of the present disclosure relate to a design for abase/interconnection device die and to designs for additional diceconnected therewith, such as a system on integrated chip (SOIC)packaging design.

In the fields of artificial intelligence (AI) and big data, digital dataincreasingly encompasses every corner of business, science, engineeringand many other disciplines. The term “big data” refers to data sets,including large, diverse, complex, longitudinal, or distributed datasets generated from instruments, sensors, Internet transactions, email,video, click streams, and all other digital sources available today andin the future. The term “big data” can also refer to data that is toolarge, too dispersed, and too unstructured to be handled using certaintypes of hardware and software facilities.

The massive scale of modern data, such as analytics data or AIprogramming, easily overwhelms memory and computation resources oncomputational servers. For example, deriving meaningful insights frombig data requires rich analytics. The big data and AI sectors demandever increasing throughput to extraordinary large volumes of data. Thisis true both with respect to the exponential rise in the volume of dataitself and to the increasingly number and complexity of formats of datathat such platforms must manage. AI and big data chipsets today arerequired to manage not just relational data, but also text, video,image, emails, social network feeds, real time data streams, sensordata, etc.

Big data is defined by the three V's: volume, velocity, and variety.Volume refers to the quantity of data being processed relative toprocessing capability. A query operation today to retrieve or process 20terabytes of data may grow to a 100 terabyte volume and beyond. Storageand the processing of vast amounts of data in a scalable fashionrequires system architectures that are capable of handling operations athigh bandwidth. Velocity describes the frequency at which data isgenerated and delivered. The velocity of large data streams face therising challenges of operations and processes to be performed inreal-time, as well as the increasing demand for such operations toidentify patterns and intents from such inputs. Variety refers to thecomplexity of different data types in addition to transactional data.The addition of unstructured data, such as speech and language,increasingly complicate the categorization of data. Delivering andprocessing such diverse data requires novel processing and memorycapabilities to efficiently serve AI and big data clients.

Embodiments of present disclosure are directed to SOIC devices andarchitecture that enables computer systems to meet the rigorous demandsthat big data places on networks, storage and servers. The embodimentsprovided herein provide devices, computer systems and methods to solvethe above problems. As noted above, modern AI and big data systemsencounter ever increasing requirement with respect to memory access andbandwidth, real time processing and data delivery, and reduced powerconsumption.

Embodiments of the present disclosure include an interconnection devicedie and SOIC architecture that addresses such problems. Embodimentsdisclosed herein are provided to reduce the distance among processorsand memories, increase the number of device-to-device (D2D) connectionsin the packaging, and provide high bandwidth (HB) memory capable ofmeeting these requirements.

A device die is provided as an interconnection device die (also referredto herein as a “base die” or “interconnection die”). The interconnectiondevice die provides a structure on which other device dice, e.g.,integrated circuit dice, such as SOICs, 3DICs, processors, or the likecan be supported and interconnected.

An integrated fan out (“InFO”) structure includes a circuit providingconnectivity in a compact design. The InFO structure can include atleast one redistribution circuit structure embedded in at least oneinsulating encapsulation of a device die, where the redistributioncircuit structure includes one or more conductors electrically connectedto conductive terminals arranged on a surface of the device die.

A system on integrated chip (“SOIC”) structure includes active dicestacked one on top of another and interconnected vertically usingthrough-silicon vias (TSVs). An SOIC can be a three-dimensionalintegrated circuit (“3DIC”). For example, a 3DIC includes a stack ofsimilar active dices, such as a stack of memory dice with a controllerlogic on a separate die (e.g., a bottom die). In some embodiments, the3DIC can include a stack of different dice. The dice can be stacked faceto back (F2B). If stacked F2B, at least two dice are stacked, one on topof the other, with their active areas facing downwards. In someembodiments, the lower die includes metallization on a back surface of asubstrate, and electrical connectors such as micro bumps, connect thetop die to this metallization. TSVs pass through the lower die'ssubstrate and connect the micro bumps on the top die, via the back-sidemetallization, to the active area of the second die. In someembodiments, the dice can be stacked face to face (F2F) in which theactive areas of the lower die and the upper die face each other withelectrical connectors providing connectivity between the dice. In a F2Fstructure, a TSV can pass through one die, such as the lower die, andmetallization or redistribution circuit can be formed on the backthereof to provide connection to components of the package.

The SOIC architecture can be electrically coupled to other device dies,such as one or more memories and/or processors. The memory stores one ormore instructions. The processor executes the one or more instructions;the one or more instructions, when executed by the processor, configurethe processor to perform data analysis and search queries.

This disclosure relates to a device, such as a computer system, thatincludes: an interconnection device die, which can be an interconnectiondevice die; at least two additional dice, which can be SOIC dice, whichlay F2F on the interconnection device die; and at least onethrough-silicon via (TSV) that enables connection to a signal line,power line or ground line, to an opposite surface of the interconnectiondevice die and to at least one electrical connector or at least oneredistribution circuit structure, which may be an integrated fan out(InFO) structure. At least one of the additional dice can be athree-dimensional (3D) integrated circuit die with F2B stacking.

Interconnection Device Die

FIGS. 1A to 1C illustrate a device die 100. Device die 100 can be abase/interconnection device die. As shown in FIG. 1A and described ingreater detail below in FIGS. 1B and 1C, device die 100 includeselectrical connectors 110 and a redistribution circuit structure 120arranged to confer a number of benefits applicable to big data and AIapplications. Specifically, as shown in FIG. 1A, a first surface 100A ofdevice die 100, for example a top or face surface, includes electricalconnectors 110. A second surface 100B of device die 100, for example abottom or back surface, includes an opening of one or morethrough-silicon vias (TSVs) 130.

Electrical connectors 110 can be formed of a conductive material, suchas metal, and configured in any suitable shape and dimension. Electricalconnectors 110 can include ball-type, bump connectors, metal pads, orany other suitable types of connectors. Electrical connectors 110(within dashed box 115) can be arranged to provide connectivity throughdevice die 100. For example, electrical connectors 110 can enableconnectivity between separate device die connected through theinterconnection device die or between the device die and an externalcircuit, terminal or the like. In some embodiments, electricalconnectors 110 can be formed of a material that includes copper and canbe configured in a round shape, such as a circle. Electrical connectors110 can have a width of between about 2 μm and about 30 μm. For example,electrical connectors 110 can have a width of about 30 μm, about 20 μm,about 10 μm, and length of about 5 μm, about 3 μm or about 2 μm. Asshown in FIG. 1B, electrical connectors 110 (within dashed box 115) canbe characterized as having a reduced pitch between electrical connectors110. A pitch refers to the spacing between two or more connectors. Forexample, in referring to FIG. 1B, a pitch 111 between electricalconnectors 110 can be between about 2 μm and about 9 μm (e.g., about 3μm, about 4 μm, about 5 μm, about 6 μm, about 7 μm, and about 8 μm). Insome embodiments, the pitch 111 between electrical connectors 110 can bebetween about 1 μm and 2 μm or less than 1 μm.

Device die 100 also includes redistribution circuit structure 120 (e.g.,an InFO structure). Redistribution circuit structure 120 can be formedof at least two metal lines or die embedded in an encapsulant (e.g., aninsulating encapsulation material), which can be a low cost materialsuch as epoxy mold compound (EMC). The lines or die are embedded in theinsulating encapsulation material with space allocated between each diefor additional I/O connection points. Thus, the redistribution circuitstructure can accommodate a high I/O count in a low cost epoxy material.The redistribution circuit can be formed using suitable vapor depositionand patterning processes to route I/O connections on the die to theperipheral mold compound regions. Miniaturizing or reducing the lengthof the connecting lines results in improved signal and power integrity(SI/PI).

FIG. 1C illustrates redistribution circuit structure 120 embedded inencapsulant 121 (e.g., an insulating encapsulation material) of devicedie 100, according to some embodiments. Redistribution circuit structure120 is electrically connected to conductive terminals (e.g., electricalconnectors 110) arranged on a surface of device die 100 (e.g., firstsurface 100A). Redistribution circuit structure 120 can includeconductive lines 120A-120G that provide electrical connections to andamong electrical connectors 110. Although a two-layer redistributioncircuit structure is shown in FIGS. 1A and 1B, redistribution circuitstructure 120 can include additional or fewer layers. Incorporation ofredistribution circuit structure 120 in device die 100 permits reducingthe dimensions of a die structure by a factor of at least 2.5. A highI/O count can thus be achieved without ceding valuable silicon (SI) areaon adjacent interconnected device dice, such as a processor or memorydie.

Referring to FIG. 1A, TSV 130 provides a channel through which anexternal line connects to the integrated circuit architecture of devicedie 100. TSV 130 is a channel that can pass completely through orpartially through device die 100. TSV 130 can be formed in any shape andsuitable dimensions. In an embodiment, TSV 130 can have a width between0.4 μm and 190 μm. In some embodiments, TSV 130 permits one or moreconnections to redistribution circuit structure 120. In someembodiments, TSV 130 permits one or more connections from second surface100B, which may have one or more electrical terminals disposed thereon,of device die 100 to electrical connectors 110 (on first surface 100A).That is, TSV 130 provides at least one connection path between oppositesides (e.g., the first surface 100A and second surface 100B sides) ofinterconnection device die 100. In some embodiments, the one or moreconnections include input/output (IO) connections, power or groundconnections, or combinations thereof, between electrical connectors 110and one or more electrical terminals disposed on second surface 100B. Asingle TSV 130 is shown in FIG. 1A; however additional TSVs can also beincluded.

In some embodiments, device die 100 can be configured to have smalldistances between device dice (e.g., channel-to-channel), which can beless than about 40 μm (e.g., less than about 30 μm, less than about 20μm, or less than about 10 μm). Accordingly, the device-to-device orchannel-to-channel distances of device die 100 can be made significantlysmaller than corresponding distances in other designs, such as a printedcircuit board (PCB) designs. Embodiments of the present disclosure cantherefore be implemented in designs that require the integration ofdensely-packed integrated circuits, such as AI and big data processingapplications.

Device die 100 confers benefits over other such designs. As describedabove, the interconnection device die configured as device die 100 canmaintain a high number of I/O connections while reducingchannel-to-channel spacing, thereby improving the critical connectionpath between system devices. For example, and as described below, thenumber of connections such as I/O connections within a given connectionarea can be improved by a factor of 2500 or more in embodiments ofdevice die 100.

The critical connection path can be defined as the connection pathlinking one system element, such as a processor or a memory device die,to other such elements. The critical connection path can also representthe connection path between such elements and external circuitryconnected to an I/O terminal of the interconnection device die. Asdescribed above, the critical connection path, the maximum path betweenany input to any output, is improved without reducing the number ofavailable I/O connections and without sacrificing SI/PI performance. Inaccordance with embodiments of this disclosure, reducing thechannel-to-channel spacing results in reduced transmission distances,which improve the latency, performance, and power consumptioncharacteristics of device die 100.

Exemplary Connector Characteristics

FIG. 2 illustrates an electrical connector 210, according to someembodiments. Electrical connector 210 can have a width (“W”) of betweenabout 2 μm and about 30 μm. In some embodiments, electrical connector210 can have a width of about 30 μm, about 20 μm, about 10 μm, andlength of about 5 μm, about 3 μm or about 2 μm.

In some embodiments, electrical connectors 210 can have a pitch of lessthan or equal to about 2 μm (e.g., about 1.5 μm, about 1 μm, and about0.5 μm). By comparison to a die structure arranged over a PCB or otherpackage substrate, the connector size of the present embodiments isreduced by a factor of at least about 15. By enhancing reducing theconnector width and pitch, the number of connectors within a surfacearea can be increased. As a result, die-to-die (e.g., between die 242and die 243) or channel-to-channel distance can be improved to be lessthan about 40 μm (e.g., about 30 μm, about 20 μm, about 10 μm, and about5 μm), according to some embodiments.

FIGS. 3A and 3B illustrate a comparison in package connection countsbetween ball connections in package design (FIG. 3A) and in a packageaccording to an SOIC architecture. The ball connectors (e.g., ballconnector pair 313) in FIG. 3A can be spaced apart about 100 μm fromeach other, for example. In FIG. 3B, a connector pitch (e.g., a pitchbetween the pair of connectors 323) in accordance with the presentdisclosure is reduced to about 2 μm or less.

By reducing the connector pitch to about 2 μm or less, the arrangementof connectors achieves a device-to-device bump grouping within a smallerarea compared to other designs. Thus, connector pitch is reduced by afactor of about 50. In this example, the channel-to-channel distance311/312 can be thereby reduced by a factor of about 50 in each direction(e.g., by a factor of fifty in the X direction and fifty in the Ydirection) such that the ratio of connectors (e.g., I/O connections) ina given area is substantially improved. Thus, in this example, thenumber of connectors arranged in a given area (X×Y) can be improved by afactor of about 2500. Embodiments of the architecture described hereincan thereby more efficiently utilize circuit area to provide increasedI/O and other integrated circuit connection among device dice andconnectivity to external devices.

SOIC Architecture Using an Interconnection Device Die

FIGS. 4A and 4B illustrate an exemplary integrated circuit package 400using device die 100. As shown in FIG. 4A, integrated circuit package400 includes package components 440 connected or bonded to device die100 through connection regions 415. Package components 440 can be devicedice that includes active devices (not shown) therein. In someembodiments, package components 440 include an SOIC die, a 3DIC die, aprocessor die, a power management die, a logic die, a communicationmanagement die (such as a baseband die), or combinations thereof.

Connection regions 415 can provide electrical connections between devicedie 100 and package components 440 through electrical connectors 110 and411, respectively. Connectors arranged in connection regions 415 caninclude ball connectors, bump connectors, solder balls, pads, or anyother type of connectors that attach device die 100 to packagecomponents 440. Connection regions 415 can include connections madethrough a hybrid bonding, flip chip or wire bonding process, or thelike. In some embodiments, electrical connectors 110 and 411 includebumps, flip chip bumps, metal pads, metal pillars (which can includecopper, tin, silver, nickel, gold, alloys thereof, composite layersthereof, or the like), metal pillars with pre-solder layers, or acombination thereof.

In this example, package components 440 of integrated circuit package400 can include memory device dice 441 and 444. Memory device dice 441and 444 can be SOICs, such as 3DICs. Specifically, memory device dice441 and 444 can each be a 3DIC memory, such as dynamic random accessmemory (DRAM) and static random access memory (SRAM). Integrated circuitpackage 400 can further include processor device dice 442 and 443. Inaccordance with FIGS. 1A to 1C, a terminal of memory device die 441 canbe connected to a terminal of processor device die 443, for example, byelectrical connectors 110 and redistribution circuit structure 120(e.g., conductors 120A to 120C). Each package component 440 can beconnected to inputs/outputs (I/Os) or other connectors through TSV 130.

TSV 130 may correspond to a single TSV or to one TSV within a pluralityof TSVs (not shown). TSV 130 may provide a via for connection of one ormore I/O connections of each package component 440 to I/O terminals ofan external device. In one example, TSV 130 may provide a channel forI/O connections of memory device die 441 to connect with anotherpackage, such as a multi-core CPU package (which may be a CPU package500 described below in FIG. 5). In addition or alternatively, TSV 130may provide a channel to provide a power or ground connection to each ofor all package components 440.

As shown in FIG. 4B, a top surface of device die 100 can include severalconnection regions 415, each connection region disposed to permitconnections of each memory device die 441 to 444 between and throughdevice die 100. As described with respect to FIG. 2, by reducing theconnector pitch to about 2 μm or less, a reduced device-to-device bumpgrouping is achieved. Here, the number of connectors arranged in theindicated area (X×Y) can be improved by a factor of about 2500 toprovide increased connectivity.

By sharing and optimizing connections via interconnection device die,integrated circuit package 400 can achieve improved performance in, forexample, big data, AI, and other applications requiring a large numberof computations and I/O connections. Device die 100 satisfies the threeVs. The package achieves reduced connector pitch and device-to-devicedistances resulting in improved volume, improves the critical connectionpath between components and to outside circuitry, thereby improvingvelocity, and enabling interconnection between a variety of packagecomponents without unduly limiting to the individual system components.

SOIC Architecture Implementation of a CPU Package Using anInterconnection Device Die

FIG. 5 illustrates a central processing unit (CPU) package 500,according to some embodiments. CPU package 500 includes processors 541to 544 connected through device die 100 by electrical connectors 510.CPU package 500 can be used in a variety of big data applications, suchas in a CPU farm.

In some embodiments, a CPU chip architecture include multipleprocessors, e.g., four, eight, or n processing cores on a devicepackage. As noted above, big data processing power can be more efficientby reducing device bandwidth, and improving high volumeinterconnections, and decreasing transmission distances. Implementingmulti-core architectures is a key to the achieving the processing powerrequired for big data. Handling ever-increasing numbers and complexitiesof calculations, image processing, logic operations requires increasedprocessing power. These requirements would otherwise strain thecapabilities of processors. Implementing multi-core architectures ondevice die 100, as described herein, enables a multi-core package thatachieves complex processing requirements while minimizing problemscaused by excess heat generation, poor bandwidth, and the like.Accordingly, a device or system can be implemented as described hereinto optimize AI and big data functions, such as processing images.

As shown in FIG. 5, according to embodiments of the present disclosure,processors 541 to 544 can share signal, power, and I/O connections, forexample, through one or more TSVs 130. In addition, processors 541 to544 can be connected to one another or to other package componentsthrough redistribution circuit structure 120. For example, processors541 to 544 can be connected to one another, to other package components,or to external connections, through electrical connectors 510,redistribution circuit structure 120, and/or TSV 130. Therefore, devicedie 100 allows a package to be achieved with an optimized connectioncount (e.g., I/O count).

As described above, the reduced connector pitch and D2D distanceachieved by packages of this disclosure enable improved transmissionspeed and reduced power consumption. For example, the D2D distance insome embodiments can be reduced to less than about 40 μm (e.g., lessthan about 30 μm, less than about 20 μm, and less than about 10 μm). Thereduced pitch, D2D distances, and routing width reduces the length of atransmission signal line between interconnected devices, therebyreducing the latency. Moreover, these improvements permit a substantialincrease in the number of I/O connections made within a device area.

Additionally, implementing several processing cores in a single devicepackage can reduce the processing burden on each processor. Moreover, inreducing the number of signal and I/O count to each connected devicedie, embodiments of the CPU chip architecture can achieve additionalimprovements with respect to thermal optimization.

CPU package 500 is different from a CPU farm using static packaging,such as a CPU farm connected through a PCB or other interposing device.As described above, a critical connection path and latency betweenpackage components can be reduced while maintaining complex andconfigurations. Moreover, CPU package 500 can be varied to accommodate anumber of package components. Although not shown, CPU package 500 caninclude other package components, such as SOIC dice, 3DIC dice,including memories, 3DIC memories, integrated processor/memory dice, orthe like. In this regard, different hierarchies of caches can be used,on the chip as well of off the chip.

In some embodiments, CPU package 500 includes processors 541 to 544 in aface to face layout with respect to device die 100 with connection viaconnectors 510 that may be hybrid bonded, for example. A face to facearrangement, where a face surface of each of processors 541 to 544 arestacked on and bonded to a face surface of device die 100. Thereby, CPUpackage 500 can be configured to permit external I/O and powerconnectivity commonly through a back surface of device die 100, e.g.,through TSV 130. Alternative embodiments can include package componentssuch as processors in a F2B arrangement as described above (not shown).

Processors 541 to 544 can thereby be efficiently disposed andinterconnected, minimizing connection paths between independentprocessors and other devices. The efficient arrangement of multipleprocessors in a multi-core package, e.g., CPU package 500, allowscomplex processing operations to be performed at reduced clock rates,reducing heat generation. Moreover, reducing D2D pitch, for example, toless than about 40 μm (e.g., less than about 30 μm, less than about 20μm, and less than about 10 μm), reduces the corresponding transmissiondistance between interconnected devices, improving latency andbandwidth.

SOIC Device Structure

FIG. 6 illustrates an SOIC structure 600, according to embodiments ofthe present disclosure. In some embodiments, SOIC structure 600 can beformed by direct die stacking and die-to-die bonding, such as by ahybrid bonding process. For example, memory dice 641 to 644 and logicdie 645 can be arranged and connected by a hybrid bonding process. TSVs630 can provide optimized interconnectivity enabling high-density,high-bandwidth, and low-power operation.

SOIC structure 600, which can be a 3DIC SRAM includes memory dice 641 to644 stacked on top of one another and interconnected vertically usingTSVs 630. In some embodiments, TSVs 630 can extend linearly orcoextensively, as shown in FIG. 6. SOIC structure 600 additionallyincludes a controller logic die 645, shown as the bottom die in thestack. Logic die 645 includes circuitry to serve as a controllerproviding processing, I/O functions, and the like. SOIC structure 600includes electrical connectors 610 connecting an active region on theface side of a first die to metallization on the back surface of asecond die. An active region of a memory die can include, for example,circuit components forming a memory array or other memory structure ineach of the memory dice 641 to 644. Metallization on the back of eachmemory dice 641 to 644 can provide I/O and other connectivity to thecircuit components. For example, an active region on the face of a firstmemory die 641 is connected through electrical connectors 610 tometallization on the back of a second memory die 642. Electricalconnectors 611 on a surface of logic die 645 connect the 3DIC stack toother package components, for example, to the interconnection devicedie.

In some embodiments, SOIC structure 600 includes TSVs 630 to achieveeffective and efficient connectivity between the individual dice andwith respect to external package components. TSVs 630 allow a criticalconnection path 631, e.g., the path from the top or outermost memory die641 to connectors 611, to pass through each die to allow addressing andsignal data to reach each memory die 641 to 644 from logic die 645.Logic die 645 can also be referred to as an application processor (AP).A 3DIC stacked in this manner and controlled through critical connectionpath 631 achieves performance improvements by providing high-density,high-bandwidth, and low-power operation. By arranging these stacks asdescribed, logic die 645 having a very wide data bus can be coupled tomemory dice stacked and having a matching wide I/O structure.

For example, as described above with respect to FIGS. 2, 4A, and 4B, thenumber of connectors arranged in a given area (X×Y) can be improved by afactor of about 2500. Thus, a very wide data bus can be achieved in agiven connection area, which may correspond to one or more connectionregions 415, as shown in FIGS. 4A and 4B. By stacking each device dievertically, a higher density memory package can be achieved by SOICstructure 600. The low D2D pitch and vertical stacking arrangementallows individual device dies (e.g., 641 and 645) to be optimallyaligned within the SOIC structure 600. As a result, optimizing routingachieves a reduction in signal latency and improved power consumption.Thereby, large memory volumes can be accessed improving memorybandwidth. In some embodiments, a bandwidth of 2.4 gigabits per second(Gbps) or higher can be achieved.

SOIC structure 600 can be connected to other package components througha common interconnection die. For example, SOIC structure can correspondto one or more package components shown in other embodiments, such asmemory device dice 441 and 444 as shown in FIGS. 4A. Specifically, logicdie 645 of SOIC structure 600 can be a lower die of memory device dice441 and 444, and connect to device die 100 by connectors 611. I/O andpower supply paths of interconnected structures can be shared throughthe common interconnection die, e.g., device die 100 by TSV 130 andredistribution circuit 120 of device die 100. By providing commoninterconnection paths, the topology of package component connections canbe improved such that a critical connection path of SOIC structure 600can be optimized. As a result, improved connection density and smallerstack sizes can be achieved.

SOIC structure 600 can include SRAM, DRAM, or other stackable memorystructure. By providing a stacked structure, memory dice and connectionscan be arranged in three dimensions, achieving a greater diversity of(and shorter) connection paths, as well as scalability. Accordingly,greater memory density, faster access times, reduced power consumption,and faster data transfer can be achieved. An SOIC, which can be 3DICSOIC, such as a 3DIC SRAM or DRAM, of this disclosure can be arrangedand packaged wafer-on-wafer. That is, two or more wafers can be formedand bonded, such that one of the wafers is flipped over and aligned withone or more of the other wafers. The flipped wafer and the adjacent,mirrored wafer can be bonded together. Package components of both waferscan be connected using TSVs, as shown in embodiments described herein.

The systems and devices described herein include an interconnectiondevice die that enables high bandwidth, low latency applications inapplications requiring extensive quantities of I/O and powerconnections. By improving SI/PI integrity and reducing the criticalconnection path of variously connected system components, the device dieimproves performance in packages, such as CPU farm or SOIC package, thatexecute big data and AI applications.

Embodiments of the present disclosure include a device with aninterconnection device die including at least one through-silicon via(TSV), at least one redistribution circuit structure, and a plurality ofelectrical connectors. The device further includes a plurality of devicedie arranged on the interconnection device die and electricallyconnected to the interconnection device die by the plurality ofelectrical connectors. The at least one redistribution circuit structureincludes one or more conductors embedded in at least one encapsulant,the one or more conductors electrically connected to conductiveterminals arranged on a first surface of the interconnection device die.The at least one device die of the plurality of device die can be athree-dimensional integrated circuit (3DIC) including one or more 3DICelectrical connectors bonded to a corresponding electrical connector ofthe plurality of electrical connectors. The at least one device die andthe interconnection device die can be arranged in a face to faceconfiguration, where the at one least TSV electrically connects at leastone device die of the plurality of device die at the first surface ofthe interconnection device die to a connection path to a second surfaceof the interconnection device die. In some embodiments, a pitch betweeneach electrical connector of the plurality of electrical connectors canbe less than or equal to about 9 μm. In some embodiments, the pluralityof electrical connectors includes at least one of ball-type electricalconnectors, bump electrical connectors, metal pad electrical connectors,or a combination thereof. The 3DIC includes a plurality of memory diestacked in a face to back (F2B) configuration. In some embodiments, the3DIC further includes a controller die, where each memory die of theplurality of memory die includes at least one TSV, and each memory diecan be connected to the controller die by a connection path through theat least one TSV. In some embodiments, the plurality of device dieincludes at least one processor arranged in a face to face configurationwith the interconnection device die, where the at least one processorcan be electrically connected to another plurality of device die throughthe interconnection device die. The 3DIC can be electrically connectedto another 3DIC by the interconnection device die. In some embodiments,a pitch between each electrical connector of the plurality of electricalconnectors can be between about 2 μm and about 9 μm, and where a widthof each electrical connector can be between about 2 μm and about 30 μm.In some embodiments, the first surface can be opposite the secondsurface of the interconnection device die.

According to some embodiments, an interconnection device die includes aplurality of electrical connectors, at least one redistribution circuitstructure, and at least one TSV. The plurality of electrical connectorscan be arranged on a surface of the interconnection device die, wherethe at least one redistribution circuit structure includes one or moreconductors embedded in at least one encapsulant, the one or moreconductors electrically connecting conductive terminals arranged on thesurface. The at least one TSV enables at least one connection from adifferent surface of the interconnection device die to one or more ofthe plurality of electrical connectors, the at least one redistributioncircuit structure, or a combination thereof. In some embodiments, theplurality of electrical connectors includes at least one of ball-typeelectrical connectors, bump electrical connectors, metal pad electricalconnectors, or a combination thereof. In some embodiments, theinterconnection device die electrically connects a first device die anda second device die through the plurality of electrical connectors, theat least one redistribution circuit structure, or a combination thereof.The at least one of the first device die and the second device die canbe a system on integrated chip (SOIC) die, where the plurality ofelectrical connectors can be arranged to connect a face of the SOIC dieto a face of the interconnection device die. The plurality of electricalconnectors can be arranged on a first surface of the interconnectiondevice die, where the at least one TSV electrically connects theplurality of electrical connectors to a connection path to a secondsurface of the interconnection device die, and the first surface can beopposite the second surface of the interconnection device die.

According to some embodiments, a system includes an interconnectiondevice die with a plurality of electrical connectors, at least oneredistribution circuit structure, and at least one TSV. A plurality ofdevice die can be arranged in a face to face configuration with theinterconnection device die, where the plurality of device die includesat least one device die that has a memory cell, and a processor coupledto the memory cell. The at least one redistribution circuit structurecan include one or more conductors embedded in at least one encapsulant,the one or more conductors electrically connected to conductiveterminals arranged on a surface of the interconnection device die. Insome embodiments, the processor, based on instructions stored in thememory cell, can be configured to perform a data query. The plurality ofelectrical connectors can be arranged on a first surface of theinterconnection device die. In some embodiments, the at least one TSVelectrically connects one or more connections from a second surface ofthe interconnection device die to one or more of the plurality ofelectrical connectors, the at least one redistribution circuitstructure, or a combination thereof. The plurality of electricalconnectors can be arranged on a first surface of the interconnectiondevice die, where the at least one TSV electrically connects theplurality of electrical connectors to a connection path to a secondsurface of the interconnection device die, and the first surface can beopposite the second surface of the interconnection device die. In someembodiments, the at least one device die includes a system on integratedchip (SOIC) device. The at least one device die can include a memorydevice having a plurality of memory die stacked in a face to back (F2B)configuration. In some embodiments, the at least one processor and theat least one device die can be arranged in a face to face configurationwith the interconnection device die, the processor can be electricallyconnected to the at least one device die through the interconnectiondevice die.

Fabrication Methods for an SOIC Architecture

According to some embodiments, FIG. 7 is an exemplary method 700 for thefabrication of an SOIC chip architecture, such as the device die andSOIC structures shown in FIGS. 1A to 1C, 4A, 4B, 5 and 6. Fabricationmethod 700 is exemplary and not limiting. Therefore, additional oralternative operations in method 700 may be performed in place of theoperations shown in FIG. 7. Further, the order of the operations ofmethod 700 shown in FIG. 7 is not limiting.

Method 700 begins with operation 702 and the formation of one or moreredistribution layers (RDLs) of a device die (which can be aninterconnection device die e.g., device die 100 of FIG. 1A). Each RDLcan be formed of a conductive material to route connections on thechip's surface (e.g., conductive lines 120A to 120G of FIG. 1A). In oneexample, each RDL can be formed by depositing and patterning theconductive material on one or more epoxy molding compound (EMC) layers,which can be EMC wafers. Each RDL can be formed by any deposition andpatterning processes. For example, a redistribution layer may be formedof a metal, metal alloy, or the like, by physical vapor deposition (PVD)metallization and electroplating processes. In some embodiments, two ormore RDLs can be formed by deposition and patterning process and stackedvertically.

Method 700 proceeds with operation 704 and the deposition of adielectric material to encapsulate the one or more RDLs. In someembodiments, the dielectric material can be an oxide-based dielectric,such as silicon oxide, deposited with plasma enhanced chemical vapordeposition or another suitable method. The dielectric material can besubsequently planarized with chemical mechanical polishing (CMP). In analternative embodiment, the dielectric material is a molding compound,such as an epoxy-based material, that is dispensed (e.g., coated) andleft to cool and harden. Once the molding compound hardens, it can bepartially grinded and polished. As a result of the aforementionedprocess, the RDLs become encapsulated in the dielectric material. Insome embodiments, the encapsulant extends across the entire surface ofthe interconnection device die. In additional embodiments, theencapsulant (e.g., encapsulant 121) provides structural support.

In referring to FIG. 7, method 700 continues with operation 706 whereone or more electrical connectors (e.g., electrical connectors110) maybe formed, prior to stacking SOIC structures on the device die, tofacilitate the mechanical and electrical coupling of the adjoiningstructures. In some embodiments, electrical connectors 110 can be formedby bonding pad structures and/or hybrid bonding structures and interfacelayers. In some embodiments, electrical connectors 110 can formed byattaching, depositing and/or patterning bump connectors, metal pads, orany other suitable types of connectors. For example, electricalconnectors 110 can be formed by depositing a material that includescopper and patterning the material in a round shape, such as a circle.

Referring to FIG. 7, method 700 continues with operation 708, where oneor more through-silicon-vias (TSVs) are formed in the device die (e.g.,device 100). Specifically, one or more contact holes are formed in thedevice die 100 by, for example, a TSV process until one or more RDLs ofthe device die 100 are exposed. Thereafter, the one or more RDLs areelectrically connected to a surface (e.g., second surface 100B) of thedevice die 100 through the contact holes. As shown in FIG. 1A, theredistribution layer 120 redistributes connections at a first surface100A and a second surface 100B of the device die.

In referring to FIG. 7, method 700 continues with operation 710, wheretwo or more device die (which may be, for example, any of SOICstructures 242 and 243 of FIGS. 2, 441 to 444 of FIGS. 4, 541 to 544 ofFIG. 5, or 645 of FIG. 6) are stacked on the device die (e.g., devicedie 100) to form an SOIC architecture structure. For example, two ormore device die can be formed by a fabrication method of an SOICstructure (described below with reference to FIG. 8). In someembodiments, the two or more device die can include at least one devicedie having a memory cell and a processor coupled to the memory cell.

According to some embodiments, FIG. 8 is an exemplary method 800 for thefabrication of an SOIC structure, such as the structures shown in 4A, 4Band 6. Fabrication method 800 is exemplary and not limiting. Therefore,additional or alternative operations in method 800 may be performed inplace of the operations shown in FIG. 8. Further, the order of theoperations of method 800 shown in FIG. 8 is not limiting.

In referring to FIG. 8, method 800 can begin with operation 802, where alogic die (e.g., logic die 645, which can be an AP) is formed byfabricating a controller chip to provide processing, I/O, and othersuitable functions. By way of example, operation 802 can include formingone or more microprocessors or CPUs to be included in the logic die.

In some embodiments, method 800 continues with operation 804, where twoor more memory die are formed. In some embodiments, operation 804includes forming a substrate including an active region, such as circuitcomponents forming a memory array or other memory structure. Operation804 can include forming the active region on a first side of a memorydie. Operation 804 can include forming electrical connectors on eachmemory die to provide I/O and other connectivity to the circuitcomponents. In some embodiments, electrical connectors can be formed byperforming metallization on a second surface of each memory die.

In referring to FIG. 8, method 800 continues with operation 806, whereone or more TSVs (e.g., TSVs 630) can be formed in memory die. In someembodiments one or more TSVs can also be formed in the logic die (e.g.,logic die 645). Specifically, one or more contact holes are formed inthe memory die (e.g., 641 to 644) and/or logic die (e.g., 645) by, forexample, a TSV process until one or more circuit structures are exposed.The one or more circuit structures can be electrically connected to orthrough an adjacent device die, as shown in FIG. 6.

In referring to FIG. 8, method 800 continues with operation 808, wheretwo or more memory die (e.g., memory die 641 to 644) and logic die(e.g., logic die 645) are stacked and bonded one on top of another.Operation 808 can include a process of planarizing and bonding contactsurfaces of the memory die using suitable bonding technologies, such ashybrid bonding, fusion bonding, anodic bonding, direct bonding, roomtemperature bonding, pressure bonding, and/or combinations thereof. Insome embodiments, the stacking operation 808 can include aligning SOICstructures via an alignment process that uses alignment marks as a guideso their respective mechanical and electrical connection points areproperly aligned when the chip layers are stacked. In some embodiments,the aligning can be performed in a separate process. In someembodiments, an active region on the face of a first memory die (e.g.,memory die 641) is connected through electrical connectors (e.g.,electrical connectors 610) to metallization on a back surface of asecond memory die (e.g., memory die 642). Subsequently, the alignedstructures are bonded to the interconnection device die to form a stack.In some embodiments, the structures are bonded by a hybrid bondingprocess.

In some embodiments, any of the planarizing, bonding, and aligningprocesses can be performed in a separate process. By way of non-limitingexample, in an alternate embodiment not shown, a fabrication method caninclude a planarizing process out of sequence from operation 808, suchas immediately after operation 804.

The foregoing disclosure outlines features of several embodiments sothat those skilled in the art may better understand the aspects of thepresent disclosure. Those skilled in the art should appreciate that theymay readily use the present disclosure as a basis for designing ormodifying other processes and structures for carrying out the samepurposes and/or achieving the same advantages of the embodimentsintroduced herein. Those skilled in the art should also realize thatsuch equivalent constructions do not depart from the spirit and scope ofthe present disclosure, and that they may make various changes,substitutions, and alterations herein without departing from the spiritand scope of the present disclosure.

What is claimed is:
 1. A method, comprising: forming a redistributionlayer on a device die; encasing the redistribution layer in anencapsulant to form a redistribution circuit structure of the devicedie; forming electrical connectors on a first surface of the device die;connecting the electrical connectors to a second surface of the devicedie by a through-silicon via (TSV) in the device die to form aninterconnection device die; and arranging a plurality of system onintegrated chip (SOIC) device dice on a first surface of theinterconnection device die, wherein at least one of the SOIC device dicecomprises a memory cell and a processor coupled to the memory cell. 2.The method of claim 1, wherein connecting the electrical connectors tothe second surface of the device die comprises forming a connection pathbetween the second surface of the interconnection device die and one ormore of the electrical connector and the redistribution circuitstructure.
 3. The method of claim 1, wherein connecting the electricalconnectors to the second surface of the device die comprises forming achannel in the device die to couple the electrical connectors to thesecond surface of the device die opposite to the first surface of theinterconnection device die.
 4. The method of claim 1, wherein arrangingthe plurality of SOIC device dice comprises arranging at least one threedimensional integrated circuit (3DIC) die on the first surface of theinterconnection device die.
 5. The method of claim 1, wherein arrangingthe plurality of SOIC device dice comprises arranging the plurality ofSOIC device dice on the first surface of the interconnection device die,each of the plurality of SOIC device dice comprising a plurality ofmemory dice stacked in a face to back (F2B) configuration.
 6. The methodof claim 1, wherein arranging the plurality of SOIC device dicecomprises arranging the plurality of SOIC device dice on the firstsurface of the interconnection device die, each of the plurality of SOICdevice dice comprising a processor, and wherein the processor and theSOIC device die are arranged in a face to face (F2F) configuration withthe interconnection device die.
 7. The method of claim 6, furthercomprising coupling the processor to the SOIC device die through theinterconnection device die.
 8. A method, comprising: forming aninterconnection device die comprising a redistribution circuit structureand a plurality of electrical connectors coupled by a through-siliconvia (TSV); arranging a plurality of device dice on the interconnectiondevice die; and coupling the device dice to the interconnection devicedie via the electrical connectors.
 9. The method of claim 8, furthercomprising insulating the redistribution circuit structure by embeddingconductors therein in an encapsulant.
 10. The method of claim 8, furthercomprising connecting the conductors to conductive terminals arranged ona first surface of the interconnection device die.
 11. The method ofclaim 8, further comprising bonding an electrical connector of a threedimensional integrated circuit (3DIC) of the plurality of device dice toa corresponding one of the plurality of electrical connectors of theinterconnection device die.
 12. The method of claim 8, furthercomprising arranging at least one the device die and the interconnectiondevice die in a F2F configuration.
 13. The method of claim 8, furthercomprising connecting the TSV between at least one of the device die ata first surface of the interconnection device die and a second surfaceof the interconnection device die.
 14. The method of claim 8, wherein apitch between adjacent electrical connectors in the plurality ofelectrical connectors is less than or equal to about 9 μm.
 15. Themethod of claim 8, wherein a width of each electrical connector of theplurality of electrical connectors is between about 2 μm and about 30μm.
 16. The method of claim 8, wherein the plurality of electricalconnectors comprise one or more of ball-type electrical connectors, bumpelectrical connectors, metal pad electrical connectors, and combinationsthereof.
 17. The method of claim 8, wherein a 3DIC of the plurality ofdevice dice comprises a plurality of memory dice stacked in a face toback (F2B) configuration.
 18. A method, comprising: forming a logic die;forming a plurality of memory dies; forming a through-silicon via (TSV)in one or more of the plurality of memory dies; stacking the logic dieand one or more of the plurality of memory dies on top of one another;aligning system on integrated chip (SOIC) structures using alignmentmarks as a guide; and bonding contact surfaces of the stacked dies toone another.
 19. The method of claim 18, further comprising connectingan active region of a first one of the plurality of memory dies throughelectrical connectors to a metallization layer on a back surface of asecond one of the plurality of memory dies.
 20. The method of claim 18,wherein bonding contact surfaces of the stacked dies comprises bondingthe contact surfaces of the stacked dies using one or more of hybridbonding, fusion bonding, anodic bonding, direct bonding, roomtemperature bonding, pressure bonding, and combinations thereof.